The present invention relates to the fabrication of integrated circuits and, more particularly, to the fabrication of integrated circuits having multilayer structures interconnected by vias (openings) etched through a polyimide layer separating such layers. Specifically, the invention relates to a process for transferring an aperture formed in a photoresist masking layer to a subsurface layer of an integrated circuit using a tapered opening etched in a polyimide layer.
The advent of very large scale integrated circuits (VLSI) and very high speed integrated circuits (VHSIC) technologies have placed stringent demands on very fine line geometry semiconductor devices as well as multilayer metal schemes requiring attendant multilayer interconnect systems. In the fabrication of semiconductor devices of high density and high complexity, it is necessary to shrink the size and spacing of device features. It is also necessary or desirable to use thick layers of insulating material to isolate between the semiconductor substrate and overlying metal layer or between multiple interconnect metal layers. Polyimide layers, in which a liquid material is applied to the surface of the semiconductor substrate and subsequently heat treated to cure or form the polyimide material, are well suited to the function of forming an insulating layer. The use of thick polyimide insulating layers, and especially on small geometry devices, presents a problem with metal continuity into contact openings. To provide desired electrical contact between interconnect layers, contact openings must be formed through the polyimide material. Metal is then applied over the device and into these contact openings. Because the polyimide may be thick, it is difficult to achieve reliable metal coverage over the peripheral walls of the contact openings to the underlying material. Metal step coverage problems are enhanced by the need for the metal patterns to consist of thin and very narrow metal strips to allow fine geometry patterning. To insure reliability utilizing step coverage into openings through the thick polyimide layer, it is imperative that the edges of the opening be tapered. It is also important, however, that the size of the opening be carefully controlled. The latter requirement results partially from the fact that the lower metal surface or device region being contacted may be small and precisely placed. If the size of the opening or via is not controlled and the opening through the polyimide material is too large, then subsequently applied metal may cause shorting between adjacent device regions. There are a number of processes which provide for either the tapering of the walls of the opening or for the control of the critical dimensions thereof, however, there has not been a production campatible etching process which simultaneously achieves both of these necessary features.
Thus, during the fabrication of fine line geometry integrated circuits, a need exists for a process to etch tapered openings through a thick insulating layer to transfer critical openings to a subsurface layer of the integrated circuit.